Fujitsu Develops Power-Saving CMOS Technology for 32nm-Generation and Beyond

(PhysOrg.com) -- Fujitsu Laboratories announced today the development of power-saving CMOS technology for logic LSI chips for 32 nanometer- (32nm-) generation and beyond. The new technology enables employment of a specific silicon crystal surface, which previously had not been applied in silicon substrates due to the crystal surface's conventionally low performance in the past, by improving its performance.

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<p><a href="http://www.physorg.com/news148666062.html">Fujitsu Develops Power-Saving CMOS Technology for 32nm-Generation and Beyond</a></p> <p>(PhysOrg.com) -- Fujitsu Laboratories announced today the development of power-saving CMOS technology for logic LSI chips for 32 nanometer- (32nm-) generation and beyond. The new technology enables employment of a specific silicon crystal surface, which previously had not been applied in silicon substrates due to the crystal surface's conventionally low performance in the past, by improving its performance. </p>