Silicon Design Chain Collaboration Demonstrates Significant 90-nanometer Total Power reduction

Industry leaders, working through the Silicon Design Chain Initiative, today announced new, silicon-validated, low-power design techniques to achieve total power savings of over 40 percent on a 90-nanometer test design. The low-power design employed an ARM1136JF-S test chip, ARM Artisan standard cell libraries and memories, Cadence Encounter design platform and TSMC's Reference Flow 5.0. Applied Materials, Inc., ARM, Cadence Design Systems, and Taiwan Semiconductor Manufacturing Company (TSMC) form the Silicon Design Chain Initiative.

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<p><a href="http://www.physorg.com/news3456.html">Silicon Design Chain Collaboration Demonstrates Significant 90-nanometer Total Power reduction</a></p> <p>Industry leaders, working through the Silicon Design Chain Initiative, today announced new, silicon-validated, low-power design techniques to achieve total power savings of over 40 percent on a 90-nanometer test design. The low-power design employed an ARM1136JF-S test chip, ARM Artisan standard cell libraries and memories, Cadence Encounter design platform and TSMC's Reference Flow 5.0. Applied Materials, Inc., ARM, Cadence Design Systems, and Taiwan Semiconductor Manufacturing Company (TSMC) form the Silicon Design Chain Initiative.</p>