Freescale, Soitec achieve 70-percent improvement in electron mobility using strained SOI technology for sub-65-nm device

Marking an important advancement in strained silicon technology for next-generation devices, Freescale Semiconductor, Inc. and the Soitec Group today announced the results of their joint development effort to optimize CMOS device performance at the sub-65-nm nodes using strained silicon-on-insulator (sSOI) engineered substrates. With device results revealing an approximate 70-percent increase in electron mobility, as well as high compatibility with existing SOI CMOS processes, the collaborative effort demonstrated that 45-nm CMOS devices built using strained SOI substrates can effectively take device performance to the next level - ultimately enabling Freescale to bring faster, more power-efficient next-generation chips to market.

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<p><a href="http://www.physorg.com/news3684.html">Freescale, Soitec achieve 70-percent improvement in electron mobility using strained SOI technology for sub-65-nm device</a></p> <p>Marking an important advancement in strained silicon technology for next-generation devices, Freescale Semiconductor, Inc. and the Soitec Group today announced the results of their joint development effort to optimize CMOS device performance at the sub-65-nm nodes using strained silicon-on-insulator (sSOI) engineered substrates. With device results revealing an approximate 70-percent increase in electron mobility, as well as high compatibility with existing SOI CMOS processes, the collaborative effort demonstrated that 45-nm CMOS devices built using strained SOI substrates can effectively take device performance to the next level - ultimately enabling Freescale to bring faster, more power-efficient next-generation chips to market.</p>