SEMATECH Identifies Top Technical Challenges for 2006; Adds Transistor Scaling

SEMATECH today announced its Top Technical Challenges for 2006, continuing to underscore advanced gate stack, 193 nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics with process compatibility. Consortium leaders also placed planar bulk transistor scaling on the list for the first time.

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<p><a href="http://www.physorg.com/news3804.html">SEMATECH Identifies Top Technical Challenges for 2006; Adds Transistor Scaling</a></p> <p>SEMATECH today announced its Top Technical Challenges for 2006, continuing to underscore advanced gate stack, 193 nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics with process compatibility. Consortium leaders also placed planar bulk transistor scaling on the list for the first time.</p>