Silicon Image Unveils Breakthrough Next Generation 6.0 Gb/s Serdes Technology

Silicon Image, Inc.announced its next generation multi-rate MSLPhy™ Serializer/Deserializer (SerDes) technology, an integrated circuit transceiver that converts parallel data to serial data and vice-versa, capable of operating at bandwidths from 1.5 to 6.0 Gb/s. The MSLPhy is a low-cost solution for the storage market and other future mass markets with aggressive price/performance requirements. Silicon Image will be showcasing the 6.0 Gb/s SerDes technology during the Intel Developer Forum (IDF), being held August 23-25 at Moscone Center in San Francisco.

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<p><a href="http://www.physorg.com/news6004.html">Silicon Image Unveils Breakthrough Next Generation 6.0 Gb/s Serdes Technology</a></p> <p>Silicon Image, Inc.announced its next generation multi-rate MSLPhy™ Serializer/Deserializer (SerDes) technology, an integrated circuit transceiver that converts parallel data to serial data and vice-versa, capable of operating at bandwidths from 1.5 to 6.0 Gb/s. The MSLPhy is a low-cost solution for the storage market and other future mass markets with aggressive price/performance requirements. Silicon Image will be showcasing the 6.0 Gb/s SerDes technology during the Intel Developer Forum (IDF), being held August 23-25 at Moscone Center in San Francisco. <br></p>