IMEC demonstrates feasibility of double patterning immersion litho for 32nm node

IMEC showed in collaboration with ASML the potential of double patterning 193nm immersion lithography at 1.2NA for 32nm node Flash and logic.

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<p><a href="http://www.physorg.com/news80410095.html">IMEC demonstrates feasibility of double patterning immersion litho for 32nm node</a></p> <p>IMEC showed in collaboration with ASML the potential of double patterning 193nm immersion lithography at 1.2NA for 32nm node Flash and logic.</p>