Nanotech SRAM for battery devices unveiled

Texas Instruments said the 256-kilobit SRAM (static random access memory) test device is being considered for the next generation of mobile products that will require high performance and low power consumption.

The development of the SRAM device was announced Wednesday at a conference in San Francisco.

The device was created in conjunction with the Massachusetts Institute of Technology using TI's 65-nanometer CMOS (complementary metal oxide semiconductor) process. It boasts a 0.4 volt sub-threshold with twice as less power leakage as current models that operate at 0.6 volts.

"Scaling to such low supply voltages is critical to minimum energy processing and enables Ultra-Dynamic Voltage Scaling," said MIT Professor Anantha Chanrakasan. "The goal of this ultra-low power technology is to reduce energy ... with minimal loss in system performance."

Copyright 2006 by United Press International