Hypercubes Could Be Building Blocks of Nanocomputers

As Samuel Lee and Loyd Hook from the University of Oklahoma explain, microelectronic devices are continually getting smaller and faster, in accordance with Moore’s Law. Already, integrated circuits and transistors are reaching the nanometer scale, although they still operate based on the physical properties on the macro-scale. True nanoelectronics, the researchers explain, are not just scaled down microelectronics, but devices that will be dominated by quantum properties, and will therefore require new architectures and novel structures.

“Compared to today's microcomputers, the main advantages of future nanocomputers are higher circuit density, lower power consumption, faster computation speed and more parallel and distributed computing capabilities,” Lee told PhysOrg.com.

For example, today’s integrated circuits process information in the form of a continual flow of electrons. Nano integrated circuits, however, may process individual electrons, reducing the scale and power consumption. Such circuits would require that nano logic devices be able to count single electrons, as well as the ability for parallel computing, reversibility, locality, and a three-dimensional architecture.

To address these challenges, Lee and Hook have investigated hypercubes, which researchers have previously considered as elements of nanocomputers. In their study, which will be published in a future issue of IEEE Transactions on Computers, Lee and Hook propose a variant of the classic hypercube called the “M-hypercube” that could provide a higher-dimensional layout to support the three-dimensional integrated circuits in nanocomputers.

The M-hypercube has a structure similar to a classic hypercube, which basically extends from a square to a cube to increasingly complex M-dimensional shapes. M-hypercubes (of any dimension) are composed of nodes and links. The nodes act as gates, receiving and passing electrons through, while the links act as the paths that electrons travel along.

“The unique structure of hypercubes, including M-hypercubes, has been shown to be effective in parallel computing and communication networks and provides a unique ideal intrinsic structure which fulfills many of the needs of future nanocomputing systems,” Lee said. “These needs include massively parallel and distributed processing architecture with simple and robust communication linkages.”

Unlike in classic hypercubes, M-hypercubes contain two types of nodes: state nodes, which are embedded on the “joints” of the M-hypercubes; and transmission nodes, which are embedded in the middle of the links between state nodes. In one arrangement, the researchers embedded two state nodes on each joint, both representing a single state. Each node can be turned on or off, with the transmission nodes having the ability to isolate parts of the cube from other parts when in the off state.

Depending on the number of states required by an operation, the M-hypercube can be expanded by adding extra dimensions (which contain more nodes) or constricted by reducing its dimensions. For example, if only four states are required, the logic architecture would be a 2-D hypercube (a square), which has four state nodes. In general, the number of state nodes in a hypercube is 2m, with m being the M-hypercube’s dimensionality.

“We might construct M-hypercubes of dimensions greater than three in three-dimensional space if we allow the communication linkages at the nodes of M-hypercubes to not be mutually perpendicular,” Lee explained.

For logic operations that require many states, the researchers propose a method that could reduce the dimensions of the M-hypercube by essentially decomposing the hypercube into two lower-dimensional M-hypercubes, connected in parallel. If needed, these two M-hypercubes could themselves be decomposed into still less complex M-hypercubes, reducing the number of state nodes required per state.

In another arrangement, Lee and Hook combined an M-hypercube with an N-hypercube, resulting in what they call an “MN-cell.” Due to its versatility, the device could serve as a building block for designing sequential nano logic gates of any size and complexity.

More information: Lee, Samuel C. and Loyd R. Hook IV. “Logic and Computer Design in Nanospace.” IEEE Transactions on Computers, TC-0156-0406. To be published.

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