MaskCompose enables Renesas Technology to capture reticle floorplans, wafer layouts, and fabrication data to allow fast, automated and error-free data generation within its 90 nanometer process. By using MaskCompose to improve its reticle design flow, Renesas Technology has enhanced flexibility while speeding interaction between device engineering and manufacturing. This is especially critical in today's competitive marketplace, where product life cycles can be as short as six months and the costs of integrated circuit (IC) design and masks continue to escalate.

"When looking to standardize our post layout design flows, we selected MaskCompose because of its flexibility for current and future nanometer processes," said Teruaki Harada, department manager of EDA Fundamental Technology Development Dept. at Renesas Technology Corp. "The proven ability of MaskCompose to enhance engineering efficiency and increase functionality allows us to streamline the process and reduce the risk in the critical mask-making steps that lead to first silicon."

"Renesas Technology's decision to standardize on MaskCompose for automated reticle design synthesis demonstrates their commitment to meeting the challenges of their 90 nanometer fab with innovative tools that optimize design, tapeout, and yield," said Dr. Marc Levitt, vice president, Design-for-Manufacturing at Cadence. "We're looking forward to continue working with Renesas Technology to increase yield through our broad range of industry-leading design tools."