TSMC Achieves 28nm SRAM Yield Breakthrough

“Achieving 64Mb SRAM yield across all three 28nm process nodes is striking. It is particularly noteworthy because this achievement demonstrates the manufacturing benefits of the gate-last approach that we developed for the two TSMC 28nm high-k metal gate processes,” explained Dr. Jack Sun, vice president, Research and Development at TSMC.

The TSMC 28nm development and ramp-up has remained on track since the announcement made in September of 2008. The 28LP process is expected to enter risk production at the end of Q1 of 2010, followed closely by the 28HP risk production at the end of Q2 and the 28HPL risk production in Q3.

The 28nm LP process will serve as a fast time-to-market and low cost technology ideal for cellular and mobile applications. The 28nm HP process is expected to support devices such as CPUs, GPUs, Chipsets, FPGAs, networking, video game consoles, and mobile computing applications that are performance demanding. The 28nm HPL process features low power, low leakage, and medium-high performance. It is aimed to support applications such as cell phone, smart netbook, wireless communication and portable consumer electronics that demand low leakage.

All 28nm TSMC processes feature a comprehensive design infrastructure based on the company’s Open Innovation Platform to extend the power of the technology to a broad range of differentiating products.

Source: TSMC