Silicon Image Introduces New 18 MegaPixel Camera Processor IP Core

With its high-quality 18 megapixel (MP) image signal processing (ISP) technology, the camerIC-18 is targeted for integration into digital still camera (DSC) and video System-on-a-Chip (SoC) application processors for mobile devices such as cell phones, portable multimedia players (PMPs) and netbooks.

Silicon Image’s family of camerIC IP cores offers a cost-effective and power efficient design while placing high-performance DSC features in the hands of mobile device users. The camerIC-18 supports resolutions ranging from 5MP to 18MP, all in a single low-cost/low-power design. To effectively deliver resolutions above 12MP, the camerIC-18 IP core now includes sophisticated bad pixel detection/correction and noise reduction techniques to ensure image quality even when combined with the lower cost, high-resolution CMOS sensors commonly found in mobile devices. The camerIC-18 IP core also supports wide dynamic range processing and digital image stabilization along with an extensive set of standard features including lens shade correction, auto focus measurement, auto white balance and auto exposure support by brightness measurement.

By 2013, over 95 percent of mobile phones will have an integrated digital camera, and by 2013, over 25 percent of smartphones will support 5MP or higher resolution cameras.

Traditionally, ISP technologies have been integrated into the CMOS sensor or separate application processor semiconductors. However, for resolutions at 5MP and higher, there are increased costs and inherent technical challenges associated with incorporating ISPs into the CMOS sensor. As mobile devices utilize smaller foundry processes, the growing trend is for ISP technologies to be integrated into the SoC in an effort to further reduce the cost and power consumption of mobile devices.

The camerIC-18 IP core has the imaging bandwidth to support HD, 3D, 4K and higher resolution video camcorder ISP functions. A 4K resolution camcorder design incorporating a camerIC-18 IP core and running at 30 frames per second will only require about 700k gates to be implemented in hardware and consumes as little as 125mW of power. Only 30 million instructions per second (MIPS) of CPU time are required to support this hardware design, making the camerIC-18 IP core one of the industry’s highest performing, lowest cost, lowest power consumption camera processors in the world.

Silicon Image’s family of IP cores also includes a broad range of HDMI technology solutions, including transmitters and receivers incorporating HDMI Specification Version 1.4 features, Mobile High-Definition Link (MHL) technology, Serial ATA storage (SATA), and high-definition MPEG / H.264 / VC-1 video decoder applications.

Source: Silicon Image