Researchers Validate Energy Savings of P-Bits

The validation of probabilistic bits or PBITs is most significant in the area of reduced power consumption and increased processing speeds, resulting in making computer devices run faster and more energy efficient. A PBIT is like a conventional bit in that it takes on a 0 or a 1 value, except that one is certain of its value only with a probability of p. Current hardware, using conventional bits, expends large amounts of energy calculating with absolute certainty.

“Our PBITs model is now backed by measurements of an actual probabilistic CMOS device which we call PCMOS,” said Palem, a joint professor in the Georgia Tech College of Computing and the School of Electrical and Computer Engineering and director of the Center for Research in Embedded Systems & Technology. “Our device takes advantage of noise at the quarter-micron (0.25 micron) level and uses probability to extract great energy savings. Noise and energy savings are becoming increasingly important as semiconductors approach the nanoscale.”

This ability to cope with noise is also increasingly relevant in the context of the impact of noise as devices scale to increasingly small sizes as projected by Moore’s Law—the doubling of transistors every couple of years. Palem’s approach opens up an entirely new way of overcoming this hurdle.

“Finding ways to reduce energy demands and cope with probabilistic variations in future VLSI designs, thus sustaining Moore’s Law past the next decade, is an issue faced by the entire semiconductor industry and Krishna Palem is researching novel ways to address this problem,” said Shekhar Borkar, Intel Fellow and director of circuit research for Intel’s Microprocessor Technology Lab. “I believe that Dr. Palem’s research holds great promise for the industry, and look forward to the acceleration of his work from research to development.”

“The most striking thing about the work to me is the idea that we can utilize a phenomena normally viewed as unwanted (noise on the chip) as a vehicle to address an important and limiting problem (reducing heat dissipation). There is something powerful and appealing about turning a problem into a feature!” says Ralph K. Cavin III, Ph.D., vice president for Research Operations at Semiconductor Research Corporation.

Using the physical measurements of PCMOS devices, the research team estimates that 100-fold improvements are possible to the energy consumed and performance of complex applications such as neural networks, which are used for pattern recognition and other applications such as spoken alphabet recognition programs used on cell phones. Palem announced these results at the DARPA-PACC meeting in Santa Fe, N.M on December 1-2.

Next Steps

Next, the research team would like to work on implementing a computing tile at the chip level for applications such as neural networks. Palem estimates this will take about one year to validate. Palem sees this technology being used in robotics, natural language processing, data mining, signal processing and a range of applications with a probabilistic and an embedded flavor. In addition, in bioengineering the low-power demands of this technology are promising for use in hearing aids and optical prosthetics.

“If successful, this will mean that the semiconductor industry could continue to offer increasing performance per dollar to customers and thus continue to provide society with the benefits from powerful miniaturized computing, communication, and sensing devices. I believe that the capability to continue the three decades of scaling according to Moore’s Law is important to the economic growth and vitality of the nation’s economy,” says Cavin. “I am encouraged that early data obtained from evaluation of test chips is showing good correlation with the theoretical projections made by Dr. Palem and his team.”

More information about this research is available at http://www.crest.g … pbitscurrent