Samsung Electronics Unveils Next-generation Technology Breakthroughs

Samsung revealed its development of a three-dimensional transistor process technology for 50 nm and beyond geometry bringing the die size to a quarter of what conventional memory chips cover today. The new paper moves up the introduction of three-dimensional transistor technology from the initial point of introduction estimated to be 2007.

Other next generation memory technologies were introduced; following last year’s introduction Samsung presented a high capacity 64Mb PRAM and further expanding its expertise in nano-scale memory technology, a 70nm process technology for both NOR Flash technology and low-power DRAM were introduced.

Samsung’s System LSI paper contributions continue to grow. Out of the total 22 Samsung papers selected, 8 were generated from the System LSI end. Samsung presented a new material Ruthenium as an adhesive to enhance the copper interconnection technology to secure a stable chemical vapor deposition (CVD) seed layer for copper interconnect.

The company advances further in LONOM(Localized Oxide-Nitride-Oxide Memory) technology for logic embedded flash memory with a paper introducing a new approach balancing the height difference between logic side and memory side of an embedded device, simplifying the sophisticated process steps, and moreover boosting speed, cutting power consumption and production costs bringing a more economical solution for higher business potential.

A notable approach on the System LSI front is the new concept Samsung introduced on mechanical stress engineering. Shedding light on the possibility of the effect of flickering noise, Samsung’s new paper set the stage for dispute to a new direction of development in the field of mechanical stress engineering.

The Symposia on VLSI Technology and Circuits represents one of the world’s most prestigious academic conferences specializing in semiconductors, along with the International Electron Device Meeting (IEDM) and the International Sold-State Circuits Conference (ISSCC). The event was first organized under joint US-Japanese sponsorship in 1981 and is held alternately in Honolulu and Kyoto each June.

The world’s top semiconductor makers submit hundreds of academic papers to this conference each year. The documents are strictly screened before final selection for presentation. The Highlight Session features the top papers for the year, underscoring the individual company’s technology and production expertise.

The original press release can be found here.