Samsung Announces New Diagnostic Software to Reduce Design Time for Nano-class ICs

The new software can perform simulation in the preliminary design stage, detecting any potential design errors before moving on to the prototype stage. This will result in greatly reinforcing production of high-quality memory products, a nd reducing valued development time and cost.

Samsung's ESCORT software can significantly increase wafer yield s through the careful simulation in the early stag es of the product development cycle. The Samsung SRSIM can estimate when the performance of transistors in the memory chip circuits might deteriorate after a series of designated time-lapses.

The new diagnostic processes can be applied not only to memory products, but also to display drive ICs (DDI) , CMOS image sensors (CIS) and system on chip (SoC) designs . By improving product yield and eliminating correction on mask , the ESCORT/SRSIM diagnostic software can shorten the product development time by at least four weeks, preventing unnecessary delays arising from a need to re-design the circuits . Based on the reduced design time and increased wafer yields, the new software is projected to save as much as $30 million ( U.S. ) in development costs each year.