Copper Resistivity Fixable for 45 nm Node, but Long-Term Issues Remain

Commenting on the recently concluded Copper Resistivity Workshop in Burlingame, CA, SEMATECH and Novellus interconnect specialists shared insights on results of the recent meeting, which drew approximately 160 engineers. The industry-wide workshop, co-sponsored by SEMATECH and Novellus, focused on ways to extend the use of copper in advanced semiconductors in the face of increasing copper resistivity at linewidths below 90 nm.

“Due to the fundamental laws of physics, copper resistivity is bound to increase and will result in several critical issues that need to be addressed,� said Andreas Knorr, conference co-chair and manager of the Advanced Materials Development Program in SEMATECH’s Interconnect Division. “Various process refinements could alleviate perhaps 5 to 15 percent of the problem, provided that chip manufacturers are willing to accept added cost and design complexity.�

Below 90 nm linewidths, copper resistivity rises dramatically because of increased electron scattering on grain boundaries and interfaces. These resistivity increases can sharply diminish or wipe out the capacitance benefits of low-k dielectric materials, which have long been an industry focus.

“The increase in resistivity of an ultrathin wire was of academic interest long before the first IC�, said Ron Powell, conference co-chair and Novellus fellow. “But we have been so successful at scaling down CMOS devices and wiring that we now have to consider the practical impacts of these ‘size effects’ as well.�

“Ironically, the switch from aluminum to copper wiring has accelerated the problem, since size effects show up in copper at closer-in technology nodes. Regardless of how the situation came about, it is likely to be addressed by a synergistic combination of materials, process and design changes,� Powell added. “Novellus and SEMATECH therefore conceived of a cross-functional workshop to raise awareness of the problem and drive a solution.�

At the resistivity workshop, experts sought to build consensus on the contributions and root causes of metal line resistivity increases at wire widths below 90 nm, discuss the performance and reliability impact of these surges and consider potential solutions with innovative approaches to materials, process and integration, and circuit design. Industry analyst Dan Hutcheson of VLSI Research praised the conference as “truly problem focused,� adding that it was “chock full of ideas with lots of theoretical detail to understand the mechanisms backed up with real research into potential solutions.�

Knorr and Powell said the workshop highlighted two promising “process fixes� that could moderately mitigate the effects of resistivity:

-- Minimize the volume that diffusion barriers occupy by making them ultra-thin
-- Enlarge copper grains to diminish boundaries and encourage unimpeded electron flow.

While participants believed that designers using hierarchical design rules will be able to work around the resistivity increase to reach the 45 nm node, they warned that it will be critical to minimize line resistance differences induced by process variation. These differences originate mostly with lack of adequate critical dimension (CD) control and dishing and erosion problems caused by chemical‑mechanical polishing (CMP), resulting in line cross-section variations. Also, workshop experts cautioned that reliability in fine lines will be a critical issue due to generally smaller grain sizes, and higher ratios of metal surface area to metal volume.

“The ultimate solutions will probably come in the form of short lines and a move to three-dimensional interconnect,� said Sitaram Arkalgud, SEMATECH’s Interconnect director. But he added that despite copper’s inherent problems, the workshop revealed scant support for returning to the metal it replaced several years ago.

“The entire audience was asked if they planned to move back to aluminum, and the answer was a resounding ‘No,’ � Arkalgud recalled. “Only one person suggested that it was even a possibility.�

Arkalgud said SEMATECH will continue to guide member companies and the industry in seeking effective resistivity solutions for the subsequent 32 nm and 22 nm technology nodes, including exploration of shorter lines 3D architecture. “Effective interconnect is vital to remaining on the Roadmap, and we’ll be exploring a variety of options to make sure we can offer effective solutions at the right time,� Arkalgud said.

Glenn Alers, principal engineer at the Novellus Customer Integration Center, said: “Novellus will continue to work with university groups to generate fundamental understanding of scattering mechanisms at copper interfaces, to model the impact of size effects on overall interconnect performance, and to stimulate out-of-the-box solutions. We will also be driving new processes into the industry that, among their other benefits, will reduce effective copper resistivity. For example, expect to see more use of ultrathin diffusion barriers deposited by ion induced atomic layer deposition (i-ALD) to maximize copper volume, and electrodeposition chemistries and annealing procedures to produce large copper grains in narrow trenches.�