Spansion Introduces Innovative Package-On-Package Solution To Reduce Wireless Device Size

As a result, handset manufacturers can accommodate the growing demand for advanced features in their wireless products without having to increase their size and weight.

“As wireless devices become more and more sophisticated, they require Flash memory solutions that offer increased code and data storage in a package that doesn’t increase the form factor of the end product,” said Amir Mashkoori, executive vice president of Spansion’s Wireless Solutions Division. “Just as our initial multi-chip packages helped transform the memory industry by reducing the footprint for system memory, these new PoP solutions represent the next evolution in packaging innovation.”

Spansion’s POP solutions measure approximately 1.4 mm in height and vertically combine a system memory package with a logic chip set package. PoP solutions enable a high degree of flexibility for designers, allowing virtually any POP-enabled memory package to be combined with any PoP-enabled logic chip set in a matter of weeks. PoP solutions also enable high yield utilization of both logic and memory, and simplified test to help reduce time-to-market and maximize cost efficiency.

Spansion: Driving PoP Standards, Chipset Support

Spansion takes a system-level approach to the design and delivery of Flash memory and is undertaking extensive work to foster PoP standardization. As an active member of JEDEC, Spansion leads the JC11.2 task group responsible for the PoP design guide generation. The company is also working to help ensure broad availability and interoperability of its PoP solutions through close working relationships with chipset vendors.

"Spansion's vision for an efficient and scaleable interface architecture has been integral in driving JEDEC interface standards for package on package," said Lee Smith senior director of business development for Amkor Technology, Inc. "We are now seeing tremendous interest from our customer base in combining Amkor's award winning PSvfBGA bottom logic package with Spansion's top memory package. We are seeing immediate benefits from this collaboration, and have extended our relationship with Spansion to include PoP roadmap alignment, joint stacking and board-level reliability studies, which promise to facilitate PoP adoption in a broader range of applications."

Technical Features

Spansion has the capability of delivering 8-die solutions in a 128-ball, 12 x 12 mm package with a 0.65 mm pitch. PoP’s short trace lengths and low bus capacitance also help to overcome the signal integrity and timing issues associated with emerging 133 MHz dual-data rate (DDR) memory solutions. Spansion’s approach reduces pin-count and eliminates printed-circuit board (PCB) routing between logic and memory, for reduced design complexity.

Spansion’s PoP solutions include the inherent benefits of its advanced two-bit-per-cell MirrorBit™ technology, including the right combination of reliability, cost, performance and density. With the future availability of the ORNAND™ architecture, Spansion plans to extend the benefits of MirrorBit technology and believes it will be able to respond to the demand for mass storage solutions in wireless handsets and complement application processors with an optimized code and data storage solution.

Samples of 12 x 12 mm and 15 x 15 mm Flash memory PoP solutions are available now for wireless phones and will vary in pricing depending on logic/memory densities and combinations.