Research could produce a new class of computer chip

The work is being funded by DARPA (the Defense Advanced Research Projects Agency) which recently granted a Young Faculty Award to Xinming Huang, assistant professor of electrical and computer engineering at WPI. Huang was one of only 10 researchers nationwide to receive a 2007 Young Faculty Award from the agency, whose mission is to fund high-risk research with the potential to dramatically advance traditional military roles and missions.

The 18-month, $150,000 award will support Huang’s effort to close an important technology gap that divides the two primary ways of designing and building chips to run electronic devices.

Most consumer electronics, from cell phones, to PDAs, to MP3 players, use ASIC (application-specific integrated circuit) chips, which are “hard-wired” to perform specific jobs and cannot be reprogrammed. FPGAs (field-programmable gate arrays), on the other hand, contain a general-purpose array of components that can be reprogrammed on the fly to do different tasks.

Each technology has advantages and disadvantages. ASICs are more power efficient than FPGAs, which, because the are designed to be universal, have many redundant electronic components, all of which consume power whether or not that are needed to carry out a particular application. Because they are programmed by software, rather than having their functions hard-wired into silicon, FPGAs cost a small fraction of the $1 million to $2 million it takes to design a new ASIC chip.

“For military applications, battery power is preferred, which favors ASICs,” Huang says. “But the battlefield is a dynamic environment, with constantly changing conditions. The military would like to be able to be able to continually reprogram chips in the field—for example, to dynamically change the spectrum for radio communications or to update the function of tactical sensors. Currently, this can only be done by using multiple ASICs or power-greedy FPGAs.”

Huang's reconfigurable computing device, called the smart cell, will combine the advantages of ASICs and FPGAs. It will incorporate more than a thousand individual processors wired onto a silicon substrate. Each processor will be responsible for performing a single operation, such as addition or multiplication, as data flows through the chip. Using a type of parallel computing called stream processing, the chip will complete hundreds of calculations simultaneously, enabling it to perform up to 300 times faster than microprocessors and about 15 times faster than FPGAs.

As with FPGAs, the smart cells will be programmed by software, enabling their functions to be updated continually as conditions change. But since the individual processors will be optimally design to perform specific functions, the chips will approach the power efficiency of ASICs. The architecture should scale easily, making it possible to build more powerful chips just by adding more processors.

To create the new architecture, Huang must find a way to integrate hundreds of individual processors in a single chip, something that has never been attempted before. An even more daunting task is developing a way to connect the processors to each other. “If the chip is to be truly reconfigurable, every processor must be able communicate with every other processor at any time,” Huang says. “These interconnections will be very difficult to develop, but are the key to the chip’s success.”

Source: Worcester Polytechnic Institute