Cadence Delivers 90-Nanometer Reference Flow to Optimize Nanometer Design for IBM-Chartered Process Platform

Cadence Encounter-Based Reference Flow to Provide High Quality of Silicon for Complex 90-Nanometer System-on-Chip Designs

San Jose, CA , May 24, 2004


Cadence Design Systems, Inc. (NYSE:CDN) today announced the availability of a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometer process platform. The Cadence reference flow seamlessly integrates intellectual property (IP) developed by Artisan Components, Inc. for the IBM-Chartered cross-foundry design enablement program. Developed in conjunction with IBM, this RTL-to-GDSII reference flow—based on the Cadence Encounter digital IC design platform—is optimized across the front-to-back design chain. It offers chip designers a predictable path for system-on-chip (SoC) design from RTL to first-pass silicon.