New SOI transistor developed beyond 65-nm technology nodes

20% increase in speed and 1/10 power reductions by employing back-bias control

Hitachi, Ltd. announced that it has developed a new SOI (Silicon On Insulator)^*1) transistor which dramatically improves speed and lowers power consumption, for processes beyond 65-nm technology nodes, in conjunction with Renesas Technology Corp. The transistors fabricated on SOI layers which have aggressively scaled buried oxide layer,^*2) approximately 10 nm, achieved not only increase in the drive current by 20 % but also 1/10 reductions in power consumption by using wide-range back-bias control. This transistor is expected to become a fundamental CMOS device for low-power and high-performance applications beyond the 65-nm technology nodes.