Poseidon Design Systems Introduces ESL Tools That Analyze, Optimize and Accelerate Processor-Based Designs

Triton Tool Suite Enables Designers to Trade off Performance, Power and Cost for SoCs, Platform ASICs, Structured Arrays and FPGAs

Poseidon Design Systems, Inc. today announced an Electronic System Level (ESL) tool suite - Triton Tuner(TM) and Triton Builder(TM) - that automates the process of optimizing and substantially accelerating processor-based designs. Based on a SystemC software and hardware co-simulation environment, transactional-level modeling (TLM) technology, and Poseidon's innovative HW/SW partitioning technology, the Triton tool suite enables SoC designers to co-simulate hardware and software at the architectural level, then tune and accelerate the embedded system for optimal performance, power and cost.