Hitachi, Renesas Develop Technology to Enable Interconnection of Stacked Chips at Room Temperature

The new technology enables a room-temperature bonding of 10 stacked chip layers in a package with a thickness of 1 mm or less

Hitachi, Ltd. and Renesas Technology Corp. today announced a new stacked chip technology that uses a through-hole interconnection method to enable chips to bond at room temperature. The new technology eliminates the need for wire bonding and reduces package thickness by more than 60% for the most advanced SiP (System in Package) products. The method offers a new packaging technology option for developing 3D-stacked SiP products.

Full story »

All News summaries from Technology news
All News summaries for June 02, 2005