0.4-V DRAM array technology using twin cells for next generation mobile devices

Enabling the longer retention time and fast read/write operation under low voltage condition

Hitachi, Ltd. in cooperation with Elpida Memory, Inc., have proposed a new DRAM (*1) circuit design enabling 0.4-V operation. The proposed array employs a twin cell scheme, which uses two conventional DRAM cells to store 1-bit information, and achieves a longer retention time and fast read/write operation under low voltage condition. This technology will be fundamental for designing DRAM, with its large memory capacity, as the low power memory device in next generation mobile information devices.