UMC Develops Ultimate Spacer Process to Enhance MOSFET Device Performance for 65nm and Beyond

UMC today announced that its Central Research and Development Division (CRD) has successfully developed an Ultimate Spacer Process (USP) technology that simultaneously enhances NMOS and PMOS device performance. Devices fabricated at UMC using USP exhibited drive current improvements of 15% for NMOS and 7% for PMOS, while maintaining overall process simplicity. This accomplishment is instrumental in achieving performance improvement during increasingly difficult CMOS scaling situations.