http://www.physorg.com/ en-us Physorg.com internet news portal provides the latest news on science including: Physics, Nanotechnology, Life Sciences, Space Science, Earth Science, Environment, Health and Medicine. Semiconductor and chip maker Cadence Design Systems' Israel office announced Monday it would make hiring a priority for 2006 by adding 20 percent more jobs. http://www.physorg.com/news11930.html Technology Mon, 20 Mar 2006 14:39:51 EST news11930 Cadence Design Systems, Inc. and Faraday Technology Corporation today announced that Faraday has joined the OpenChoice intellectual property (IP) program to co-develop with Cadence an extensive list of library views. The libraries are being designed to facilitate digital implementation and signal integrity (SI) under UMC's 130-nanometer Fusion process. http://www.physorg.com/news4032.html Technology Mon, 09 May 2005 15:32:50 EST news4032 Children have a remarkable ability to learn new languages. As little as five hours of exposure to a second language is enough to help infants incorporate characteristics of that language into their babbling according to a new study. http://www.physorg.com/news176458764.html Medicine & Health Tue, 03 Nov 2009 08:20:59 EST news176458764 Freescale Semiconductor and Cadence Design Systems, Inc. have signed a multi-year agreement designed to help Freescale realize competitive advantages by boosting new product design efficiency and speeding the delivery of advanced silicon products to market. http://www.physorg.com/news8163.html Technology Mon, 14 Nov 2005 14:50:34 EST news8163 Researchers in Taiwan are designing a computer for pedal cyclists that tells them when to change gear to optimize the power they develop while maintaining comfort. The system is described in the latest issue of the International Journal of Human Factors Modelling and Simulation. http://www.physorg.com/news151064058.html Technology Tue, 13 Jan 2009 10:14:18 EST news151064058 Cadence Design Systems, Inc. and the Shanghai Research Center For Integrated Circuit Design (ICC), China's first national integrated circuit (IC) design industrialization base founded by China's Ministry of Science and Technology, today announced the availability of the ICC-Cadence CPU/digital signal processing (DSP) system-on-chip (SoC) reference methodology. The reference methodology, which includes the Cadence© Encounter digital implementation platform, Incisive(TM) functional verification platform and CoWare software tools for electronic system-level design and verification, is the first to offer rapid and predictable implementation of SoC chip designs for the expanding IC industry in China. http://www.physorg.com/news1019.html Technology Tue, 31 Aug 2004 12:32:25 EST news1019 Cadence Encounter-Based Reference Flow to Provide High Quality of Silicon for Complex 90-Nanometer System-on-Chip Designs San Jose, CA , May 24, 2004 Cadence Design Systems, Inc. (NYSE:CDN) today announced the availability of a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometer process platform. The Cadence reference flow seamlessly integrates intellectual property (IP) developed by Artisan Components, Inc. for the IBM-Chartered cross-foundry design enablement program. Developed in conjunction with IBM, this RTL-to-GDSII reference flow -based on the Cadence Encounter digital IC design platform -is optimized across the front-to-back design chain. It offers chip designers a predictable path for system-on-chip (SoC) design from RTL to first-pass silicon. http://www.physorg.com/news113.html Technology Wed, 26 May 2004 01:04:22 EST news113 Cadence Encounter Digital IC Design Platform Delivers First Pass Silicon and Fast Time-to-Market for Complex Leading-Edge Design Cadence Design Systems, Inc. today announced that the Cadence(R) Encounter(TM) digital IC design platform has helped ATI Technologies Inc. implement the world's fastest, most powerful visual processor technology. Using the Cadence Encounter technologies in combination with its first-class design team, ATI achieved first pass silicon success of its critically-acclaimed Radeon X800 family of high-speed graphics chips, while besting previous industry records for performance, power efficiency, and compactness. http://www.physorg.com/news441.html Technology Wed, 21 Jul 2004 08:39:14 EST news441 Cadence Design Systems, Inc. today announced that technology giant NEC Corp. used the Cadence Encounter digital IC design platform to develop the complete 90-nanometer chipset for one of the world's fastest vector supercomputers.With Encounter technology, NEC achieved a 2x improvement in chip performance on its most advanced, highest performance 90-nanometer vector supercomputer chipset to date. The NEC SX-8 chipset is comprised of four 90-nanometer designs, including a hierarchical 9-million instance chip that was routed flat for final engineering change order implementation and rapid design closure. http://www.physorg.com/news2342.html Technology Mon, 13 Dec 2004 12:30:20 EST news2342 New Library Views Support Next-Generation Low Power Devices Artisan Components and Cadence Design Systems, Inc. today announced their collaboration to provide library views that enable designers to more effectively optimize low-power chip designs. The companies have partnered to create and qualify Artisan library views based on the Cadence(R) effective current source model (ECSM) format. These views provide customers with accurate delay prediction across a wide range of voltage levels and operating conditions using the Cadence Encounter(TM) digital IC design platform. http://www.physorg.com/news1443.html Technology Mon, 04 Oct 2004 11:47:16 EST news1443 Cadence Design Systems, Inc. today announced Cadence Encounter Test Architect, the industry's first full-chip test architecture development product. It includes the industry's first unified compiler-based methodology for full-chip test. The result is faster development of a higher-quality test infrastructure than is currently possible with point test tools.Based on a unique test infrastructure compiler, Encounter Test Architect supports a unified methodology for specifying, compiling, and verifying full-chip test. This includes scan, compression, memory BIST, on-product clock generation, boundary scan, and I/O test. http://www.physorg.com/news3286.html Technology Mon, 07 Mar 2005 14:10:30 EST news3286 Cadence Design Systems, Inc. today announced that Renesas Technology Corp. has standardized on MaskCompose(TM) for automated reticle design synthesis in its 90 nanometer design flow. MaskCompose provides a highly efficient and design tapeout system, automatically generating jobdecks, order forms and customized paperwork. This reduces costly errors and poor mask revisions in manufacturing caused by human errors in the tape-out process. http://www.physorg.com/news1407.html Technology Thu, 30 Sep 2004 12:11:33 EST news1407 Industry leaders, working through the Silicon Design Chain Initiative, today announced new, silicon-validated, low-power design techniques to achieve total power savings of over 40 percent on a 90-nanometer test design. The low-power design employed an ARM1136JF-S test chip, ARM Artisan standard cell libraries and memories, Cadence Encounter design platform and TSMC's Reference Flow 5.0. Applied Materials, Inc., ARM, Cadence Design Systems, and Taiwan Semiconductor Manufacturing Company (TSMC) form the Silicon Design Chain Initiative. http://www.physorg.com/news3456.html Technology Mon, 21 Mar 2005 13:45:45 EST news3456 A $100 million partnership has been made to create what collaborators consider will be the world's most powerful university-based supercomputing center. http://www.physorg.com/news66667126.html Nanotechnology Fri, 12 May 2006 15:38:46 EST news66667126 System-Level Design Knowledge Reduces Verification Effort by Up to 50%San Jose, CA , June 1, 2004 -- Cadence Design Systems, Inc. and CoWare(R) Inc., the leading supplier of system-level electronic design automation (EDA) software and services, announced the availability of an integrated, seamless flow from electronic system-level (ESL) design through verification for complex system-on-chip (SoC) designs. The ESL design-for-verification solution-which marks a major milestone on the strategic alliance roadmap between the companies-enables customers to capture system-level design knowledge and apply it later in the design process to reduce verification time by up to 50%. The flow is based on new integration between the latest releases of CoWare's SystemC-based ConvergenSC(TM) SoC design tools and ConvergenSC Model Library and the Cadence(R) Incisive(TM) functional verification platform. http://www.physorg.com/news142.html Technology Thu, 03 Jun 2004 01:10:11 EST news142