<?xml version="1.0" encoding="iso-8859-1"?>
<?xml-stylesheet type="text/xsl" href="http://www.physorg.com/tmpl/default/css/default/feedRSS.xsl"?>
<rss version="2.0">
<channel>
<title>PHYSorg.com: PHYSorg news tagged with: memory bus</title>
<link>http://www.physorg.com/</link>
<language>en-us</language> 
<description>Physorg.com internet news portal provides the latest news on science including: Physics, Nanotechnology, Life Sciences, Space Science, Earth Science, Environment, Health and Medicine.</description>

 <item>
     <title>More chip cores can mean slower supercomputing, simulation shows</title>
   	 <description>(PhysOrg.com) -- The worldwide attempt to increase the speed of supercomputers merely by increasing the number of processor cores on individual chips unexpectedly worsens performance for many complex applications, Sandia simulations have found.</description>
     <link>http://www.physorg.com/news151158992.html</link>
	 <category>Technology</category>
	 <pubDate>Wed, 14 Jan 2009 12:36:32 EST</pubDate>
	 <guid isPermaLink="false">news151158992</guid>
</item>


</channel>
</rss>

