Search results for +"MOSFET" :
 Rensselaer student invents alternative to silicon chipEven before Weixiao Huang received his doctorate from Rensselaer Polytechnic Institute, his new transistor captured the attention of some of the biggest American and Japanese automobile companies. The 2008 ... |
NXP announces world's smallest high-performance MOSFETNXP Semiconductors, the independent company founded by Philips, today announced a new range of small signal MOSFET devices housed in one of the world’s smallest packages, the SOT883. Boasting an ultra-small 1.0 x 0.6 mm footprint, ... |
 SEMATECH and NIST Collaborate on Chemical Analysis of Advanced Gate DielectricsNitrogen incorporation in thin HfO2/SiO2 film systems representative of high-k gate dielectric layers in advanced metal-oxide semiconductor field-effect transistors (MOSFETs) has been ... |
 Researchers shine light on atomic transistorResearchers from TU Delft and the FOM Foundation (Netherlands) have successfully measured transport through a single atom in a transistor. This research offers new insights into the behaviour of so-called dopant ... |
Sematech to Investigate Alternate Channel Materials for Advanced MicrochipsPushed by the scaling limits of silicon-based devices, Sematech engineers have launched a project to investigate alternative materials to Si in MOSFET channels, the critical pathways that allow electrical signals to flow ... |
 New design for transistors powered by single electronsScientists have demonstrated the first reproducible, controllable silicon transistors that are turned on and off by the motion of individual electrons. The experimental devices, designed and fabricated at NTT ... |
Freescale creates first commercially viable GaAs MOSFET deviceFreescale Semiconductor has developed the industry's first device that combines the high performance of gallium arsenide (GaAs) semiconductor compounds with the advantages of traditional metal oxide semiconductor field effect ... |
 Penn-State Philips CMOS transistor model adopted as industry-wide standard for future nanometer chip designPhilips and the Pennsylvania State University today announced that their jointly developed PSP (Penn State Philips) complementary metal-oxide semiconductor (CMOS) transistor model has been selected by the Compact ... |
UMC Develops Ultimate Spacer Process to Enhance MOSFET Device Performance for 65nm and BeyondUMC today announced that its Central Research and Development Division (CRD) has successfully developed an Ultimate Spacer Process (USP) technology that simultaneously enhances NMOS and PMOS device performance. Devices fabricated ... |
World's first SOI MOSFET with crystalline Gd2O3Researchers at AMICA have successfully fabricated the world's first MOSFETs on ultra-thin-body silicon-on-insulator (SOI) material with a crystalline gadolinium oxide (Gd2O3) gate dielectric. |
Sensors, a smart dose of medicine for cancer treatmentNov 02, 2005 | pda version
New sensor systems being developed will help treat cancer and improve the accuracy and reliability of existing radiation treatments. They should help improve patient care and outcomes. The results will go straight to commercialisation ... |
NEC Develops Highly-Reliable CMOSFET with Phase Controlled NiSi (NFET) & Ni3Si (PFET) Gate ElectrodeNEC Corporation ("NEC") today announced the development of a transistor featuring a new gate stack structure using a hafnium ("Hf")-based, high-k dielectric and a metal gate electrode, which simultaneously realize significant ... |
Freescale, University of Florida advance Moore's lawJun 01, 2005 | pda version
Industry’s first double-gate transistor model enables smaller, more powerful silicon products that use less energy
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New mathematical model better describes transistor behaviorPenn State and Philips researchers have merged the best features of their respective approaches to produce a new mathematical model that describes the behavior of the MOS transistor in a wide class of integrated circuits ... |
SEMATECH Identifies Top Technical Challenges for 2006; Adds Transistor ScalingSEMATECH today announced its Top Technical Challenges for 2006, continuing to underscore advanced gate stack, 193 nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics with process compatibility. Consortium ... |
